UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1000

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
D.1 Major Revisions in This Edition
Remark “Classification” in the above table classifies revisions as follows.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Throughout
CHAPTER 1 OUTLINE
p.19
p.30
CHAPTER 5 CLOCK GENERATOR
p.228
p.233
pp.235 to 238 Change of Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned
pp.247 to 253 Change of 5.6.5 CPU clock status transition diagram
pp.254, 255
CHAPTER 8 WATCHDOG TIMER
pp.386, 387
CHAPTER 10 A/D CONVERTER
Throughout
pp.398, 399,
401, 409, 416
p.399
p.420
p.422
CHAPTER 11 D/A CONVERTER
pp.428, 429
CHAPTER 12 OPERATIONAL AMPLIFIER
p.438
CHAPTER 14 SERIAL ARRAY UNIT
p.459
p.571
Page
−
−
−
−
−
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change URL of Renesas Electronics website
Change product names to A version (
Deletion of target from the capacitance value of the capacitor connected to the REGC pin
Change names of A/D conversion modes
• conversion mode 1 → normal mode 1
• conversion mode 2 → normal mode 2
• conversion mode 3 → low voltage mode
Addition of description of 20 MHz internal high-speed oscillation clock oscillator
Change of 1.2 Ordering Information
Change the value of vectored interrupt sources of 78K0R/LF3
Change of description of the wait time of the FSEL
Change of 5.4.3 Internal high-speed oscillator
On (When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1)) and Figure
5-14. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI
Default Start Function Enabled Is Set (Option Byte: LVIOFF = 0))
Change of 5.6.6 Condition before changing CPU clock and processing after changing CPU
clock
Change of 8.4.3 Setting window open period of watchdog timer
Deletion of TBD from operation stabilization time 1
Change of voltage boost circuit stabilization time (TBD) to (10
Addition of Note 4 to Table 10-2. A/D Conversion Time Selection
Deletion of TBD from the output impedance within 1 kΩ of the analog input source
Change of Table 10-8. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
Change of wait time to 20
Change of turn-on time (TBD) to 20
Change of Caution 3 of Figure 14-8. Format of Serial Data Register mn (SDRmn)
Change of Caution of 14.7.5 Calculating transfer rate
μ
s or more and deletion of TBD from the settling time (18
APPENDIX D REVISION HISTORY
μ
μ
s (MAX.)
PD78F150xA)
Description
μ
s of A/D voltage comparator
μ
s)
APPENDIX D REVISION HISTORY
μ
s (MAX.))
Classification
(d)
(b)
(b)
(b)
(d)
(a)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(b)
(c)
(c)
−
(1/3)
1000