UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 17

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
<R>
<R>
peripheral functions such as ROM/RAM, LCD controller/driver, A/D converter, D/A converter, operational amplifier,
multifunctional serial interfaces, multifunctional timers, real-time counter, and watchdog timer.
1.1 Features
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
78K0R/Lx3
RENESAS MCU
The 78K0R/Lx3 microcontrollers are 16-bit single-chip microcontrollers that include the 78K0R CPU core and
Minimum instruction execution time can be changed from high speed (0.05
system clock) to ultra low-speed (61
General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
ROM, RAM capacities
On-chip internal high-speed oscillation clock
• 20 MHz internal high-speed s oscillation clock: 20 MHz ± 2.4 %
• 8 MHz internal high-speed s oscillation clock: 8 MHz ± 2 % (when 1.8 V≤V
• 1 MHz internal high-speed s oscillation clock: 1 MHz ± 13 %
On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
Self-programming (with boot swap function/flash shield window function)
On-chip debug function
On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
On-chip watchdog timer (can operate on dedicated internal low-speed oscillation clock)
On-chip multiplier/divider (16 bits × 16 bits, 32 bits ÷ 32 bits)
On-chip key interrupt function
On-chip clock output/buzzer output controller (output: 2)
On-chip BCD adjustment
I/O ports:
• 78K0R/LF3: 51
• 78K0R/LG3: 67 (N-ch open drain: 2)
• 78K0R/LH3: 83 (N-ch open drain: 2)
Timer
64 KB
96 KB
128 KB
16-bit timer
Watchdog timer
Real-time counter
Program Memory
(ROM)
Timer
4 KB
6 KB
7 KB
Data Memory
(RAM)
12 ch
(input: 6, output: 6)
1 ch
1 ch (output:2)
μ
s: @ 32.768 kHz operation with subsystem clock)
CHAPTER 1 OUTLINE
78K0R/LF3
μ
μ
μ
PD78F1500A
PD78F1501A
PD78F1502A
78K0R/LF3
80 pins
12 ch
(input: 8, output: 8)
78K0R/LG3
μ
μ
μ
PD78F1503A
PD78F1504A
PD78F1505A
78K0R/LG3
100 pins
μ
s: @ 20 MHz operation with high-speed
DD
<2.7 V)
12 ch
(input: 12, output: 12)
μ
μ
μ
78K0R/LH3
PD78F1506A
PD78F1507A
PD78F1508A
78K0R/LH3
128 pins
R01UH0004EJ0401
Jul 2, 2010
Rev.4.01
17

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