UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 613

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM (bit 3 of IICA control register 0 (IICCTL0)) = 1, an interrupt request occurs at the falling edge of
Remark
2. When there is a chance that arbitration will occur, set SPIE = 1 for master device operation.
the ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt request
occurs at the falling edge of the eighth clock.
SPIE: Bit 4 of IICA control register 0 (IICCTL0)
Status During Arbitration
Table 15-4. Status During Arbitration and Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
CHAPTER 15 SERIAL INTERFACE IICA
Note 2
Note 2
Note 1
Note 1
Note 1
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