UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 602

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
15.4.2 Setting transfer clock by using IICWL and IICWH registers
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(1) Setting transfer clock on master side
(2) Setting IICWL and IICWH on slave side
Caution Note the minimum f
Remarks 1. Calculate the rise time (t
At this time, the optimal setting values of IICWL and IICWH are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
• When the standard mode
(The fractional parts of all setting values are truncated.)
• When the fast mode
• When the standard mode
Transfer clock =
IICWL =
IICWH = (
IICWL =
IICWH = (
IICWL = 1.3
IICWH = (1.2
IICWL = 4.7
IICWH = (5.3
operation frequency for serial interface IICA is determined according to the mode.
2. IICWL: IICA low-level width setting register
Standard mode:
Fast mode:
differ depending on the pull-up resistance and wire load.
IICWH: IICA high-level width setting register
t
t
f
F
R
CLK
:
:
Transfer clock
Transfer clock
Transfer clock
Transfer clock
:
μ
μ
IICWL + IICWH + f
μ
μ
s × f
s × f
0.52
0.47
s − t
s − t
SDA0 and SCL0 signal falling times
SDA0 and SCL0 signal rising times
0.48
0.53
CPU/peripheral hardware clock frequency
CLK
CLK
R
R
− t
− t
F
F
) × f
) × f
CLK
× f
× f
f
f
f
− t
− t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
R
R
operation frequency when setting the transfer clock. The minimum f
− t
− t
= 3.5 MHz (MIN.)
= 1 MHz (MIN.)
CLK
R
F
F
) and fall time (t
) × f
) × f
(t
R
CLK
CLK
+ t
F
)
F
) of the SDA0 and SCL0 signals separately, because they
CHAPTER 15 SERIAL INTERFACE IICA
602
CLK