UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 81
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 81 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
3.1 Memory Space
maps.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Products in the 78K0R/Lx3 microcontrollers can access a 1 MB memory space. Figures 3-1 to 3-3 show the memory
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
Data memory
space
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 Security Setting).
When boot swap is used:
Program
memory
space
F F F F F H
F F F 0 0 H
F E F 0 0 H
F E E F F H
F 1 0 0 0 H
F 0 F F F H
F 0 8 0 0 H
F 0 7 F F H
F 0 0 0 0 H
E F F F F H
1 0 0 0 0 H
0 F F F F H
F F E F F H
F F E E 0 H
F F E D F H
0 0 0 0 0 H
Figure 3-1. Memory Map (
General-purpose register
Special function register (SFR)
function register (2nd SFR)
Extended special
32 bytes
Flash memory
CHAPTER 3 CPU ARCHITECTURE
RAM
55.75 KB
256 bytes
Reserved
Reserved
Mirror
64 KB
4 KB
2 KB
Note 1
IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
μ
PD78F1500A, 78F1503A, 78F1506A)
0 1 0 C D H
0 1 0 C 4 H
0 1 0 C 3 H
0 1 0 0 0 H
0 0 F F F H
0 0 0 C E H
0 0 0 C D H
0 0 0 C 4 H
0 0 0 C 3 H
0 0 0 C 0 H
0 0 0 B F H
0 0 0 8 0 H
0 0 0 7 F H
0 0 0 0 0 H
0 F F F F H
0 1 0 C E H
0 1 0 C 0 H
0 1 0 B F H
0 1 0 8 0 H
0 1 0 7 F H
On-chip debug security
On-chip debug security
CHAPTER 3 CPU ARCHITECTURE
Option byte area
Option byte area
ID setting area
ID setting area
CALLT table area
CALLT table area
Vector table area
Vector table area
Program area
Program area
128 bytes
128 bytes
64 bytes
64 bytes
10 bytes
10 bytes
4 bytes
4 bytes
Note 2
Note 2
Note 2
Note 2
0 1 F F F H
Boot cluster 0
Boot cluster 1
Note 3
81
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