UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 456

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
(4) Serial communication operation setting register mn (SCRmn)
SCRmn
Symbol
SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception
mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data
length.
Rewriting SCRmn is prohibited when the register is in operation (when SEmn = 1).
SCRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0087H.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Figure 14-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/3)
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I
DAP
TXE
TXE
mn
mn
mn
15
0
0
1
1
0
0
1
1
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20)
RXE
CKP
RXE
mn
mn
mn
14
0
1
0
1
0
1
0
1
Does not start communication.
Reception only
Transmission only
Transmission/reception
DAP
mn
13
CKP
mn
12
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
11
Selection of data and clock phase in CSI mode
0
EOC
mn
10
D7 D6 D5 D4 D3 D2 D1 D0
PTC
mn1
D7 D6 D5 D4 D3 D2 D1 D0
Setting of operation mode of channel n
9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PTC
mn0
8
After reset: 0087H
DIR
mn
7
6
0
2
CHAPTER 14 SERIAL ARRAY UNIT
C mode.
SLC
mn1
5
R/W
SLC
mn0
4
3
0
DLS
mn2
2
Type
DLS
mn1
1
2
3
4
1
DLS
mn0
0
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