UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 296

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.4 Channel Output (TOpq pin) Control
6.4.1 TOpq pin output circuit configuration
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Interrupt signal of the master channel
Interrupt signal of the slave channel
The following describes the TOpq pin output circuit.
<1> When TOMpq = 0 (toggle mode), the set value of the TOLp register is ignored and only INTTMpr (slave
<2>
<3> When TOEpq = 1, INTTMpq (master channel timer interrupt) and INTTMpr (slave channel timer interrupt) are
<4> When TOEpq = 0, writing to TOpq bit to the target channel (TOpq signal) becomes valid. When TOEpq = 0,
<5> The TOp register can always be read, and the TOpq pin output level can be checked.
channel timer interrupt) is transmitted to the TOp register.
INTTMpr (slave channel timer interrupt) are transmitted to the TOp register.
At this time, the TOLp register becomes valid and the signals are controlled as follows:
When INTTMpq and INTTMpr are simultaneously generated, (0% output of PWM), INTTMpr (reset signal)
takes priority, and INTTMpq (set signal) is masked.
transmitted to the TOpq register. Writing to the TOp register (TOpq write signal) becomes invalid.
When TOEpq = 1, the TOpq pin output never changes with signals other than interrupt signals.
To initialize the TOpq pin output level, it is necessary to set TOEpq = 0 and to write a value to TOpq.
neither INTTMpq (master channel timer interrupt) nor INTTMpr (slave channel timer interrupt) is transmitted
to TOpq register.
When TOMpq = 1 (combination operation mode), both INTTMpq (master channel timer interrupt) and
When TOLpq = 0: Forward operation (INTTMpq → set, INTTMpr → reset)
When TOLpq = 1: Reverse operation (INTTMpq → reset, INTTMpr → set)
(INTTMpq)
(INTTMpr)
Figure 6-26. Output Circuit Configuration
<1>
<2>
TOLpq
TOMpq
TOEpq
<3>
TOpq write signal
<4>
TOp register
Set
Reset/toggle
<5>
CHAPTER 6 TIMER ARRAY UNIT
Internal bus
TOpq pin
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