UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 985

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Serial
interface
IICA
LCD
controller/d
river
Function
If other I
communications
are already in
progress
STT, SPT: Bits
1, 0 of IICA
control register 0
(IICCTL0)
Reserving
transmission
LCDMD: LCD
mode register
LCDM: LCD
display mode
register
Details of
Function
2
C
If I
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I
sequence.
<1> Clear bit 4 (SPIE) of IICCTL0 to 0 to disable generation of an interrupt request
<2> Set bit 7 (IICE) of IICCTL0 to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL) of IICCTL0 to 1 before ACK is returned (4 to 80 clocks after
Setting STT and SPT (bits 1 and 0 of IICCTL0) again after they are set and before
they are cleared to 0 is prohibited.
When transmission is reserved, set SPIE (bit 4 of IICTL0) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IICA after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE to 1 when MSTS (bit 7 of IICS) is
detected by software.
Bits 0 to 3, 6 and 7 must be set to 0.
When LCD display is not performed or necessary, set SCOC and VLCON to 0, in
order to reduce power consumption.
When the external resistance division method has been set (MDSET1 = MDSET0 =
0), do not set VLCON to 1.
Set BLON and LCDSEL to 0 when 8 has been selected as the number of time slices
for the display mode.
To use the internal voltage boosting method, specify the reference voltage by using
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
2
C operation is enabled and the device participates in communication already in
signal (INTIICA) when the stop condition is detected.
setting IICE to 1), to forcibly disable detection.
2
C communications. To avoid this, start I
Cautions
APPENDIX C LIST OF CAUTIONS
2
C.
2
C in the following
2
C
p.621
p.621
p.621
p.672
p.673
p.673
p.673
p.673
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