UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 805

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
V
V
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-
Remark V
POR
PDR
(when X1 oscillation
oscillation clock (f
Internal high-speed
Internal reset signal
system clock (f
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
2.
3.
4.
5.
6.
1.8 V
CPU
VOLTAGE DETECTOR).
V
V
(V
MX
V
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by using an
option byte (option byte: LVIOFF = 0).
The reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation
accuracy stabilization time of the internal high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
This is a preliminary value and subject to change.
LVI
POR
PDR
Note 1
IH
Note 6
Note 6
0 V
Operation
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
LVI
DD
)
)
:
)
: POC power supply fall detection voltage
: POC power supply rise detection voltage
stops
LVI detection voltage
Wait for oscillation
accuracy stabilization
(about 2.1 to 5.8 ms)
0.5 V/ms (MIN.)
Reset processing
specified by software
Starting oscillation is
Note 2
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
and Low-Voltage Detector (1/2)
Note 5
(oscillation
Reset
period
Reset processing (about 195 to 322 ms)
stop)
Wait for oscillation
accuracy stabilization
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
DD
Normal operation
specified by software
Starting oscillation is
≤ 5.5 V. To make the state at lower than 1.8 V reset state
Note 4
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Note 5
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
(about 2.1 to 5.8 ms)
Reset processing
specified by software
Starting oscillation is
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 5
Operation stops
805