UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 586

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.2 Configuration of Serial Interface IICA
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Serial interface IICA includes the following hardware.
(1) IICA shift register (IICA)
(2) Slave address register (SVA)
IICA is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock.
IICA can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IICA.
Cancel the wait state and start data transfer by writing data to IICA during the wait period.
IICA can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Cautions 1. Do not write data to IICA during data transfer.
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
SVA can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD = 1 (while the start condition is detected).
Reset signal generation clears SVA to 00H.
Address: FFF50H
2. Write or read IICA only during the wait period. Accessing IICA in a communication state other
3. When communication is reserved, write data to IICA after the interrupt triggered by a stop
Symbol
IICA
than during the wait period is prohibited. When the device serves as the master, however,
IICA can be written only once after the communication trigger bit (STT) is set to 1.
condition is detected.
Registers
Control registers
Item
7
Table 15-1. Configuration of Serial Interface IICA
Figure 15-3. Format of IICA Shift Register (IICA)
After reset: 00H
6
IICA shift register (IICA)
Slave address register (SVA)
Peripheral enable register 0 (PER0)
IICA control register 0 (IICCTL0)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port mode register 6 (PM6)
Port register 6 (P6)
5
R/W
4
Configuration
3
CHAPTER 15 SERIAL INTERFACE IICA
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