UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 580

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note1
SE
10
0
1
0
1
0
78K0R/Lx3
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark X: Don’t care
MD
102
0
0
1
0
0
1
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table 14-
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer to
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
MD
101
0
1
0
0
1
0
10). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
m (SOm).
Table 14-10).
condition is generated.
condition is generated.
SOE
10
0
0
1
1
0
1
1
1
0
1
1
1
0
Note4
Note4
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SO
10
1
1
1
CKO
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
10
1
1
1
1
1
TXE
10
Table 14-9. Relationship between register settings and pins
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
(Channel 0 of unit 1: CSI20, UART2 transmission, IIC20)
RXE
10
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
Note3
Note3
PM
10
×
1
1
1
0
0
0
×
0
0
0
0
0
P10 PM
Note3
Note3
×
×
×
×
1
1
1
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note2
11
×
1
×
1
1
×
1
×
0
0
0
0
0
P11
Note2
Note3
Note3
Note3
Note3
×
×
×
×
×
×
×
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
PM
12
×
×
0
0
×
0
0
0
×
×
×
×
×
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
P12
×
×
1
1
×
1
1
1
×
×
×
×
×
transmission/reception
transmission/reception
IIC20 address field
Operation mode
transmission
Operation stop
start condition
Master CSI20
Master CSI20
stop condition
Slave CSI20
Slave CSI20
transmission
transmission
transmission
Master CSI20
Slave CSI20
transmission
IIC20 data
IIC20 data
reception
reception
reception
UART2
mode
IIC20
IIC20
CHAPTER 14 SERIAL ARRAY UNIT
Note5
SCL20/P10
(output)
(output)
(output)
SCK20/
SCK20
SCK20
SCK20
SCK20
SCK20
SCK20
SCL20
SCL20
SCL20
SCL20
SCL20
(input)
(input)
(input)
P10
P10
Pin Function
RxD2/INTP6/
RxD2/INTP6/
RxD2/INTP6/
SI20/SDA20/
INTP6/P11
INTP6/P11
INTP6/P11
INTP6/P11
P11
SDA20
SDA20
SDA20
SDA20
SDA20
SI20
SI20
SI20
SI20
P11
P11
Note2
TO02/P12
TO02/P12
TO02/P12
TO02/P12
TO02/P12
TO02/P12
TO02/P12
TO02/P12
TO02/P12
SO20/
TxD2/
SO20
SO20
SO20
SO20
TxD2
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