UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 317

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.7.3 Operation as frequency divider
from TOpq.
detected. If MDpq0 of TMRpq = 0 at this time, INTTMpq is not output and TOpq is not toggled. If MDpq0 of TMRpq = 1,
INTTMpq is output and TOpq is toggled.
TCRpq loads the value of TDRpq again, and continues counting.
of the TOpq output.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The timer array unit can be used as a frequency divider that divides a clock input to the TIpq pin and outputs the result
The divided clock frequency output from TOpq can be calculated by the following expression.
TCRpq operates as a down counter in the interval timer mode.
After the channel start trigger bit (TSpq) is set to 1, TCRpq loads the value of TDRpq when the TIpq valid edge is
After that, TCRpq counts down at the valid edge of TIpq. When TCRpq = 0000H, it toggles TOpq. At the same time,
If detection of both the edges of TIpq is selected, the duty factor error of the input clock affects the divided clock period
The period of the TOpq output clock includes a sampling error of one period of the operation clock.
TDRpq can be rewritten at any time. The new value of TDRpq becomes valid during the next count period.
Remark
• When rising edge/falling edge is selected:
• When both edges are selected:
Clock period of TOpq output = Ideal TOpq output clock period ± Operation clock period (error)
Divided clock frequency = Input clock frequency/{(Set value of TDRpq + 1) × 2}
Divided clock frequency ≅ Input clock frequency/(Set value of TDRpq + 1)
TIpq pin
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
TSpq
detection
Edge
Figure 6-45. Block Diagram of Operation as Frequency Divider
Timer counter
Data register
(TCRpq)
(TDRpq)
CHAPTER 6 TIMER ARRAY UNIT
controller
Output
TOpq pin
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