UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 538

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
14.6.2 UART reception
device (start-stop synchronization).
the odd- and even-numbered channels must be set.
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remarks 1. f
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
UART reception is an operation wherein the 78K0R/Lx3 microcontrollers asynchronously receive data from another
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2. For 78K0R/LF3, UART0 is not mounted.
UART
f
MCK
CLK
: System clock frequency
: Operation clock (MCK) frequency of target channel
Channel 1 of SAU0
RxD0
INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
INTSRE0
• Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
5, 7 or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Appending 1 bit
MSB or LSB first
MCK
UART0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
Channel 3 of SAU0
RxD1
INTSR1
INTSRE1
UART1
CLK
Channel 1 of SAU1
RxD2
INTSR2
INTSRE2
/(2 × 2
CHAPTER 14 SERIAL ARRAY UNIT
11
UART2
× 128) [bps]
Note
Channel 3 of SAU1
RxD3
INTSR3
INTSRE3
UART3
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