UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 663

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 15-33 are explained below.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
Remark <1> to <19> in Figure 15-33 represent the entire procedure for communicating data using the I
<3> If the address received matches the address of a slave device
<4> The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
<5> The timing at which the master device sets the wait status changes to the 8th clock (WTIM = 0).
<6> The slave device writes the data to transmit to the IICA shift register (IICA) and releases the wait status that
<7> If the master device releases the wait status (WREL = 1), the slave device starts transferring data to the
<8> The master device sets a wait status (SCL0 = 0) at the falling edge of the 8th clock, and issues an interrupt
<9> The master device reads the received data and releases the wait status (WREL = 1).
<10> The ACK is detected by the slave device (ACKD = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and the slave device issue
<12> The slave device writes the data to transmit to the IICA register and releases the wait status that it set by
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)
the addresses match.
it set by the slave device.
master device.
(INTIICA: end of transfer). The master device then sends an ACK by hardware to the slave device.
an interrupt (INTIICA: end of transfer).
the slave device. The slave device then starts transferring data to the master device.
Figure 15-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 15-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 15-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
CHAPTER 15 SERIAL INTERFACE IICA
Note
, that slave device sends an ACK by
2
C bus.
Note
when
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