UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 818

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(b) When LVI default start function enabled is set (LVIOFF = 0)
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Caution Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
Figure 24-6 shows the timing of the internal reset signal generated by the low-voltage detector.
Start in the following initial setting state.
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When starting operation
When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: V
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
Set bit 0 (LVIF) of LVIM to 0 (“Supply voltage (V
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
This is due to the fact that while the pulse width detected by LVI must be 200
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
1 is set upon reset occurrence, and the CPU starts operating without waiting for the LVI
stabilization time.
DD
) ≥ detection voltage (V
CHAPTER 24 LOW-VOLTAGE DETECTOR
LVI
)”)
LVI
= 2.07 V ±0.1 V ).
μ
s max., LVION =
DD
))
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