UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 336

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Operation
start
During
operation
Operation
stop
TAU stop
Remarks 1.
Sets TOEmp (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
Set values of the TMRmn and TMRmp registers and
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
Set values of the TDRmn and TDRmp registers can be
changed after INTTMmn of the master channel is
generated.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers cannot be
changed.
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
TOEmp of slave channel is cleared to 0 and value is set
to the TOmp register.
To hold the TOmp pin output levels
When holding the TOmp pin output levels is not
necessary
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Switches the port mode register to input mode.
2.
3.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
Clears TOmp bit to 0 after the value to
be held is set to the port register.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
Figure 6-61. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
The counter of the master channel loads the TDRmn
value to TCRmn, and counts down. When the count
value reaches TCRmn = 0000H, INTTMmn output is
generated. At the same time, the value of the TDRmn
register is loaded to TCRmn, and the counter starts
counting down again.
At the slave channel, the value of TDRmp is loaded to
TCRmp, triggered by INTTMmn of the master channel,
and the counter starts counting down. The output level of
TOmp becomes active one count clock after generation of
the INTTMmn output from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
The TOmp pin outputs the TOmp set level.
The TOmp pin output levels is held by port function.
The TOmp pin output levels go are into Hi-Z output state.
TEmn = 1, TEmp = 1
TEmn, TEmp = 0, and count operation stops.
Power-off status
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
TCRmn and TCRmp hold count value and stops.
The TOmp output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
336