UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1009

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
3rd Edition
Edition
Addition of description to 6.7.1 Operation as interval timer/square wave output
Modification of Figure 6-37 Block Diagram of Operation as Interval
Timer/Square Wave Output
Addition of (2) When the timer input (TIpq pin input, f
selected as count clock to Figure 6-39 Example of Set Contents of Registers
During Operation as Interval Timer/Square Wave Output
Modification of Figure 6-40 Operation Procedure of Interval Timer/Square Wave
Output Function (1/2)
Modification of Caution in Figure 7-3 Format of Real-Time Counter Control
Register 0 (RTCC0)
Addition of description to 7.3 (8) Hour count register (HOUR)
Addition of description to Figure 7-14 Format of Watch Error Correction Register
(SUBCUD)
Modification of Figure 7-26 512 Hz or 16.384 kHz Output Setting Procedure
Addition of Caution 3 to Figure 9-2 Format of Clock Output Select Register n
(CKSn)
Modification of Remark in 9.4.1 Operation as output pin
Modification of Figure 9-4 Remote Control Output Application Example
Addition of Notes 2, 3 to and modification of Cautions 1, 2 in Figure 10-4 Format
of A/D Converter Mode Register (ADM)
Modification of Table 10-2 A/D Conversion Time Selection
Modification of description in 10.3 (4) Analog reference voltage control register
(ADVRC)
Modification of Figure 10-8 Format of Analog Reference Voltage Control
Register (ADVRC)
Addition of <3> to and modification of <8> and Caution 4 in 10.4.1 Basic
operations of A/D converter
Modification of Figure 10-16 Software trigger mode (Continuous conversion
mode)
Modification of Figure 10-17 Software trigger mode (Single conversion mode)
Modification of <2> in 10.4.3 (3) Timer trigger mode (Continuous conversion
mode)
Modification of Figure 10-18 Timer trigger mode (Continuous conversion mode)
Modification of <2> in and addition of <5> to 10.4.3 (4) Timer trigger mode (Single
conversion mode)
Modification of Figure 10-19 Timer trigger mode (Single conversion mode)
Addition of <3> to and modification of <8>, <11> and Caution 7 in setting methods of
10.4.3 A/D converter operation modes
Modification of 10.6 (1) Operating current in STOP mode and (12) Rewriting
DACSWn during A/D conversion
Modification of Figure 11-1 Block Diagram of D/A Converter
Addition of Note 1 to and modification of Note 2 and Remark in Figure 11-3
Format of D/A Converter Mode Register (DAM)
Modification of Caution in Figure 11-4 Format of D/A Conversion Value Setting
Registers W0 and W1 (DACSW0, DACSW1)
Modification of <3>, <6> in and addition of Cautions 1, 2 to 11.4.1 Operation in
normal mode
Modification of <3>, <6>, <9> in and addition of Cautions 1 to 3 to 11.4.2
Operation in real-time output mode
Modification of (3) in 11.5 Cautions for D/A Converter
Description
SUB
/4, f
SUB
/2 or INTRTCI) is
APPENDIX D REVISION HISTORY
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 9 CLOCK
OUTPUT/BUZZER
OUTPUT
CONTROLLER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 D/A
CONVERTER
Chapter
(7/11)
1009