UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 300

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(b) Set/reset timing
Master channel
Remarks 1. to_reset: TOpq pin reset/toggle signal
Slave channel
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at master channel timer interrupt
(INTTMpq) generation is delayed by 1 count clock by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave channels are set as follows.
• Master channel: TOEpq = 1, TOMpq = 0, TOLpq = 0
• Slave channel:
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
to_set:
<1> 78K0R/LF3:
<2> 78K0R/LG3:
<3> 78K0R/LH3:
(Internal signal)
(Internal signal)
(Internal signal)
Count clock
TOpq pin/
INTTMpq
TOpr pin/
INTTMpr
to_reset
to_reset
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
to_set
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 3 (where r is a consecutive integer greater than q)
TOpq
TOpr
f
TOpq pin set signal
CLK
TOEpr = 1, TOMpr = 1, TOLpr = 0
Figure 6-31. Set/Reset Timing Operating Statuses
Delays to_reset by 1 count
clock with slave channel
Toggle
Set
CHAPTER 6 TIMER ARRAY UNIT
Reset
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