UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 675

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Symbol
Address: FFF43H
78K0R/Lx3
VLCD
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Cautions 1. Bits 3, 6, and 7 must be set to 0.
Remark f
Note These settings are prohibited because V
(4)
LCD boost level control register (VLCD)
This register is used to select the reference voltage that is to be generated when operating the voltage boost
circuit (contrast adjustment). The reference voltage can be selected from 20 stages.
VLCD is set using an 8-bit memory manipulation instruction.
Reset signal generation sets VLCD to 0FH.
VLCD4
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
2. Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost method has
f
CLK
SUB
been set.
:
:
After reset
CPU/Peripheral hardware clock frequency
Subsystem clock frequency
VLCD3
Figure 16-5. Format of LCD Boost Level Control Register (VLCD)
:
6
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0FH
Other than above
R/W
VLCD2
5
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
LC0
VLCD4
VLCD1
> 5.5 V.
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VLCD3
VLCD0
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CHAPTER 16 LCD CONTROLLER/DRIVER
(contrast adjustment)
1.75 V
1.70 V
1.65 V
1.60 V
1.55 V
1.50 V
1.45 V
1.40 V
1.35 V
1.30 V
1.25 V
1.20 V
1.15 V
1.10 V
1.05 V
1.00 V
(default)
0.95 V
0.90 V
0.85 V
0.80 V
Setting prohibited
Reference voltage
VLCD2
selection
2
VLCD1
5.25 V
5.10 V
4.95 V
4.80 V
4.65 V
4.50 V
4.35 V
4.20 V
4.05 V
3.90 V
3.75 V
3.60 V
3.45 V
3.30 V
3.15 V
3.00 V
2.85 V
2.70 V
2.55 V
2.40 V
1/3 bias
1
V
LC0
Setting
prohibited
5.20 V
5.00 V
4.80 V
4.60 V
4.40 V
4.20 V
4.00 V
3.80 V
3.60 V
3.40 V
3.20 V
voltage
1/4 bias
VLCD0
0
Note
675