UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 311

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
Remark mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
Sets the TAU0EN or TAU1EN bits of the PER0
register to 1.
Sets the TPSm register.
Sets the TMRmn register (determines operation mode of
channel).
If timer input is selected for the count clock, set the timer
input (TIpq pin input, f
the TISpq, SDIV, and RTCISpq bits.
Sets interval (period) value to the TDRmn register.
To use the TOpq output
Sets TOEpq to 1 (only when operation is resumed).
Sets the TSmn bit to 1.
Set values of TMRmn, TOMp, and TOLp registers cannot
be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOp and TOEp registers can be
changed.
The TTmn bit is set to 1.
TOEpq is cleared to 0 and value is set to TOp register.
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
Determines clock frequencies of CKm0 and CKm1.
Clears the TOMpq bit of the TOMm register to 0
(toggle mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
Sets TOEpq to 1 and enables operation of TOpq.
Clears the port register and port mode register to 0.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
SUB
/4, f
SUB
/2, or INTRTCI) by using
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmn pin goes into Hi-Z output state.
The TOpq default setting level is output when the port mode
register is in the output mode and the port register is 0.
TOpq does not change because channel stops operating.
The TOpq pin outputs the TOpq set level.
TEmn = 1, and count operation starts.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of TDRmn is loaded to TCRmn again and
the count operation is continued. By detecting TCRmn =
0000H, INTTMmn is generated and TOmn performs toggle
operation.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
The TOpq pin outputs the TOpq set level.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDRmn is loaded to TCRmn at the count clock
input. INTTMmn is generated and TOpq performs toggle
operation if the MDmn0 bit of the TMRmn register is 1.
TCRmn holds count value and stops.
The TOpq output is not initialized but holds current status.
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
311