UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1004

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
2nd Edition
Edition
Modification of Table 5-5 Changing CPU Clock
Modification of Table 5-6 Maximum Time Required for Main System Clock
Switchover, f
f
ratio), and Table 5-9 Maximum Number of Clocks Required in f
Addition of chapter
Modification of Table 7-1 Configuration of Real-Time Counter
Modification of Figure 7-1 Block Diagram of Real-Time Counter
Modification of Figure 7-2 Format of Peripheral Enable Register 0 (PER0)
Modification of Figure 7-3 Format of Real-Time Counter Control Register 0
(RTCC0)
Modification of Figure 7-4 Format of Real-Time Counter Control Register 1
(RTCC1)
Addition of Caution 3 to Figure 7-5 Format of Real-Time Counter Control
Register 2 (RTCC2)
Modification of (7) Minute count register (MIN) to (9) Day count register (DAY)
Modification of (11) Month count register (MONTH) to (13) Watch error correction
register (SUBCUD)
Addition of (17) Port mode register 3 (PM3)
Modification of Note 2 in Figure 7-19 Procedure for Starting Operation of Real-
Time Counter
Addition of 7.4.2 Shifting to STOP mode after starting operation
Addition of 7.4.8 Example of watch error correction of real-time counter
Modification of Figure 10-1 Block Diagram of A/D Converter
Modification of Figure 10-3 Format of Peripheral Enable Register 0 (PER0)
Addition of Note 1 to Figure 10-4 Format of A/D Converter Mode Register (ADM)
Addition of Table 10-2 A/D Conversion Time Selection
Modification of (4) Analog reference voltage control register (ADVRC)
Modification of Figure 10-10 Format of 8-bit A/D Conversion Result Register
(ADCRH)
Modification of Table 10-4. Setting Functions of ANI0/AMP0-/P20,
ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25, ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins, Table 10-5. Setting Functions of ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins, and Table 10-7. Setting
Functions of ANI15/AV
Addition of (12) Rewriting DACSWn during A/D conversion to 10.6 Cautions for
A/D Converter
Modification of Figure 11-1 Block Diagram of D/A Converter
Modification of Figure 11-2 Format of Peripheral Enable Register 0 (PER0)
Modification of Remark in Figure 11-3 Format of D/A Converter Mode Register
(DAM)
Addition of Caution to Figure 11-4 Format of D/A Conversion Value Setting
Registers W0 and W1 (DACSW0, DACSW1)
Addition of <1> to 11.4.1 Operation in normal mode and 11.4.2 Operation in real-
time output mode
Addition of (3) to 11.5 Cautions for D/A Converter
MAINC
↔ f
MAINC
SUBC
(changing the division ratio), f
↔f
SUBC
REFM/
, Table 5-7 Maximum Number of Clocks Required in
P157 Pin
Description
SUBC
↔ f
SUBC
(changing the division
MAINC
↔ f
APPENDIX D REVISION HISTORY
SUBC
CHAPTER 5 CLOCK
GENERATOR
(continuation)
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 D/A
CONVERTER
Chapter
(2/11)
1004