UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 269

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F00F0H
(1) Peripheral enable register 0 (PER0)
(2) Timer clock select register m (TPSm)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, writing to a
TPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of TPSm, and CKm0 is selected by bits 3 to 0.
Rewriting of TPSm during timer operation is possible only in the following cases.
Rewriting of PRSm00 to PRSm03 bits: Possible only when all the channels set to CKSmn = 0 are in the operation
Rewriting of PRSm10 to PRSm13 bits: Possible only when all the channels set to CKSmn = 1 are in the operation
TPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TPSm can be set with an 8-bit memory manipulation instruction with TPSmL.
Reset signal generation clears this register to 0000H.
Remark mn: Unit number + Channel number
Note 78K0R/LG3, 78K0R/LH3 only
TAU0EN
RTCEN
control register of the timer array unit is ignored, and all read values are default values.
<7>
m = 0, 1, mn = 00 to 07, 10 to 13
0
1
After reset: 00H
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
DACEN
Figure 6-5. Format of Peripheral Enable Register 0 (PER0)
<6>
R/W
ADCEN
<5>
stopped state (TEmn = 0)
stopped state (TEmn = 0)
IICAEN
Control of timer array unit input clock
<4>
Note
SAU1EN
<3>
CHAPTER 6 TIMER ARRAY UNIT
SAU0EN
<2>
TAU1EN
<1>
TAU0EN
<0>
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