UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 995

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Regulator
Option
byte
Function
RMC: Regulator
mode control
register
000C2H/010C2H Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is
000C0H/010C0H Set the same value as 000C0H to 010C0H when the boot swap operation is used
000C1H/010C1H Set the same value as 000C1H to 010C1H when the boot swap operation is used
000C2H/010C2H Set FFH to 010C2H when the boot swap operation is used because 000C2H is
000C3H/010C3H Set the same value as 000C3H to 010C3H when the boot swap operation is used
000C0H/010C0H The watchdog timer continues its operation during self-programming of the flash
000C1H/010C1H
000C3H/010C3H Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Setting of option
byte
Details of
Function
A wait is required to change the operation speed mode control register (OSMC) after
changing the RMC register. Wait for 2 ms by software when setting to low-power
consumption mode and 10
the procedure shown below.
• When setting to low-power consumption mode
• When setting to normal power mode
used).
because 000C0H is replaced by 010C0H.
because 000C1H is replaced by 010C1H.
replaced by 010C2H.
because 000C3H is replaced by 010C3H.
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed.
consideration.
Be sure to set bits 7 to 3 to “1”.
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
Be sure to set 000010B to bits 6 to 1.
To specify the option byte by using assembly language, use OPT_BYTE as the
relocation attribute name of the CSEG pseudo instruction. To specify the option byte
to 010C0H to 010C3H in order to use the boot swap function, use the relocation
attribute AT to specify an absolute address.
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
<1> Select a frequency of 1 MHz for f
<2> Set RMC to 5AH (set the regulator to low-power consumption mode).
<3> Wait for 2 ms.
<4> Set FLPC and FSEL of OSMC to 1 and 0, respectively.
<1> Set RMC to 00H (set the regulator to normal power mode).
<2> Wait for 10
<3> Change FLPC and FSEL of OSMC.
<4> Change the f
μ
Set the overflow time and window size taking this delay into
s.
CLK
frequency.
μ
s when setting to normal power mode, as described in
Cautions
CLK
.
APPENDIX C LIST OF CAUTIONS
μ
s
p.833
p.834
p.834
p.834
p.834
p.835
p.836
p.837
p.837
p.837
p.838
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