UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 554

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remarks 1. X: Don’t care
Notes 1. When changing the clock selected for f
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the f
Register
SMRmn
CKSmn
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 =
00FFH).
(main system clock, subsystem clock), by operating the interval timer for which f
selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and
selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When
changing f
0
1
PRS
m13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
CLK
PRS
, however, SAUm and TAU0 must be stopped as described in Note 1 above.
m12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
Other than above
PRS
m11
Table 14-3. Selection of operation clock
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
SPSm Register
PRS
m10
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
PRS
m03
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
PRS
m02
CLK
0
0
0
0
1
1
1
1
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
(by changing the system clock control register (CKC) value),
PRS
m01
0
0
1
1
0
0
1
1
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
PRS
m00
0
1
0
1
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0,
INTTM03 if m = 1
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0,
INTTM03 if m = 1
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CHAPTER 14 SERIAL ARRAY UNIT
Operation Clock (MCK)
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
f
Note2
Note2
CLK
= 20 MHz
Note1
SUB
CLK
/4 has been
frequency
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