UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 992

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Power-on-
clear
circuit
Low-
voltage
detector
Function
Timing of
generation of
internal reset
signal (LVIOFF =
1)
Timing of
generation of
internal reset
signal (LVIOFF =
0)
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-
voltage detection
level select
register
Details of
Function
−
Input voltage from external input pin (EXLVI) must be EXLVI < V
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset
signal is not released until the supply voltage (V
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 24 LOW-VOLTAGE DETECTOR).
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 24 LOW-VOLTAGE DETECTOR).
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
reset and released from the reset status. In this case, the time from release of reset
to the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, be sure to clear (0) LVION by using a 1-bit memory manipulation
instruction.
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (V
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(V
Be sure to clear bits 4 to 7 to “0”.
Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
• When changing the value after setting to the mode used as an interrupt (LVIMD =
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (V
0)
EXLVI
because an LVIIF flag may be set when LVI operation is enabled.
because an LVIIF flag may be set when the LVIS register is changed.
)) is generated and LVIIF may be set to 1.
DD
EXLVI
) is less than or equal to the detection voltage (V
) is fixed. Therefore, setting of LVIS is not necessary.
Cautions
POR
DD
, V
) fluctuates for a certain period in the
DD
PDR
) exceeds 2.07 V ±0.2 V.
APPENDIX C LIST OF CAUTIONS
), the system may be repeatedly
LVI
) (if LVISEL = 1, input
DD
.
pp.803,
804
p.803
p.805
p.806
p.807
p.812
p.812
p.812
p.813
p.814
p.814
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