UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 988

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Interrupt
functions
DMA
controller
Function
Priority
Response time
Operation in
standby mode
DMA pending
instruction
Operation if
address in
general-purpose
register area or
other than those
of internal RAM
area is specified
IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H:
Interrupt request
flag registers
Details of
Function
During DMA transfer, a request from the other DMA channel is held pending even if
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows. (See Table 18-2.)
The DMA controller operates as follows in the standby mode.
Even if a DMA request is generated, DMA transfer is held pending immediately after
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
The address indicated by DRA0n is incremented during DMA transfer. If the address
is incremented to an address in the general-purpose register area or exceeds the
area of the internal RAM, the following operation is performed.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
general-purpose register area.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag may
be set by noise.
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each.
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
Cautions
APPENDIX C LIST OF CAUTIONS
(See Table 18-3.)
p.743
p.743
p.744
p.744
p.744
p.753
Page
(28/39)
988