UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 719

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
17.4 Operations of Multiplier/Divider
17.4.1 Multiplication operation
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
• Initial setting
• During operation processing
• Operation end
• Next operation
Operation clock
<1> Set bit 7 (DIVMODE) of the multiplication/division control register (MDUC) to 0.
<2> Set the multiplicand to the multiplication/division data register A (L) (MDAL).
<3> Set the multiplier to the multiplication/division data register A (H) (MDAH).
<4> Wait for at least one clock. The operation will end when one clock has been issued.
<5> Read the product (lower 16 bits) from the multiplication/division data register B (L) (MDBL).
<6> Read the product (higher 16 bits) from the multiplication/division data register B (H) (MDBH).
<7> To execute multiplication operation next, start from the “Initial setting” for multiplication operation.
<8> To execute division operation next, start from the “Initial setting” in 17.4.2 Division operation.
Remark
DIVMODE
MDAH
MDBH
MDAL
(There is no preference in the order of executing steps <2> and <3>. Multiplication operation is automatically
started when the multiplier and multiplicand are set to MDAH and MDAL, respectively.)
(There is no preference in the order of executing steps <5> and <6>.)
Steps <1> to <7> correspond to <1> to <7> in Figure 17-6.
"0"
Figure 17-6. Timing Diagram of Multiplication Operation (0003H × 0002H)
<1>
Initial value
Initial value
Initial value
= 0
= 0
= 0
<2>
<3>
<4>
0003H
0002H
0006H
<5>, <6>
CHAPTER 17 MULTIPLIER/DIVIDER
<7>
1FFFEH
FFFFH
FFFFH
FFFE000H
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