UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 344

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.8.3 Operation as multiple PWM output function
following expressions.
the TOmp pin. TCRmp loads the value of TDRmp to TCRmp, using INTTMmn of the master channel as a start trigger,
and start counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and stops counting until the next start trigger
(INTTMmn of the master channel) has been input. The output level of TOmp becomes active one count clock after
generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H.
the duty factor, and outputs a PWM waveform from the TOmq pin. TCRmq loads the value of TDRmq to TCRmq, using
INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmq = 0000H, TCRmq outputs
INTTMmq and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output
level of TOmq becomes active one count clock after generation of INTTMmn from the master channel, and inactive when
TCRmq = 0000H.
the same time with timer array unit 0 and up to three types with timer array unit 1.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
By extending the PWM function and using two or more slave channels, many PWM output signals can be produced.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
TCRmn of the master channel operates in the interval timer mode and counts the periods.
TCRmp of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
In the same way as TCRmp of the slave channel 1, TCRmq of the slave channel 2 operates in one-count mode, counts
When channel 0 is used as the master channel as described above, up to seven types of PWM signals can be output at
Caution To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1, write access is
Remarks 1.
Remark
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmp (slave 2)}/{Set value of TDRmn (master) + 1} × 100
2.
3.
necessary at least twice. Since the values of TDRmn and TDRmp are loaded to TCRmn and TCRmp
after INTTMmn is generated from the master channel, if rewriting is performed separately before and
after generation of INTTMmn from the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both the
registers immediately after INTTMmn is generated from the master channel (This applies also to
TDRmq of the slave channel 2) .
Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
78K0R/LF3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
CHAPTER 6 TIMER ARRAY UNIT
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