UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 444
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 444 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
14.1 Functions of Serial Array Unit
14.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20)
14.1.2 UART (UART0, UART1, UART2, UART3)
(R
rate). Full-duplex UART communication can be realized by using two channels, one dedicated to transmission (even
channel) and the other to reception (odd channel).
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
X
Each serial interface supported by the 78K0R/Lx3 microcontrollers has the following features.
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
[Clock control]
[Interrupt function]
[Error detection flag]
This is a start-stop synchronization function using two lines: serial data transmission (T
[Data transmission/reception]
[Interrupt function]
[Error detection flag]
The LIN-bus is accepted in UART3 (2 and 3 channels of unit 1)
[LIN-bus functions]
D) lines. It transmits or receives data in asynchronization with the party of communication (by using an internal baud
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
• Transfer end interrupt/buffer empty interrupt
• Overrun error
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
• Framing error, parity error, or overrun error
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
External interrupt (INTP0) or timer array unit (TAU) is
used.
CHAPTER 14 SERIAL ARRAY UNIT
X
D) and serial data reception
444
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