UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 272

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
TMRmn
Symbol
Remark
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
MAS
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use the odd channel as a slave channel (MASTERmn = 0).
Clear MASTERmn to 0 for a channel that is used with the independent operation function.
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
TER
CKS
STS
mn2
mn1
CIS
mn
mn
Other than above
15
0
1
0
0
0
1
0
0
1
1
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
Operates as slave channel with combination operation function.
Operates as master channel with combination operation function.
STS
mn1
mn0
CIS
14
0
0
1
0
0
1
0
1
0
Falling edge
Rising edge
Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
STS
mn0
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (2/4)
13
0
1
0
0
0
Only software trigger start is valid (other trigger sources are unselected).
Valid edge of TIpq pin input signal, f
and capture trigger.
Both the edges of TIpq pin input signal, f
and a capture trigger.
Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the combination operation function).
Setting prohibited
CCS
mn
12
Selection of valid edge of TIpq pin input signal , f
(the timer input used with channel x is selected by using TISm register).
MAST
ERmn
11
STS
mn2
10
Selection of slave/master of channel n
Setting of start trigger or capture trigger of channel n
STS
mn1
9
STS
mn0
8
After reset: 0000H
SUB
mn1
CIS
/2, f
7
SUB
SUB/
/2, f
mn0
CIS
4, or INTRTC1 is used as both the start trigger
6
SUB/
4, or INTRTC1 are used as a start trigger
CHAPTER 6 TIMER ARRAY UNIT
5
0
R/W
SUB
/2, f
4
0
SUB/
4, or INTRTC1
mn3
MD
3
mn2
MD
2
mn1
MD
1
mn0
MD
0
272