UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 878

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Instruction
Bit
manipulate
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
Mnemonic
XOR1
SET1
CLR1
SET1
CLR1
NOT1
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
register (CKC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, ES:[HL].bit
saddr.bit
sfr.bit
A.bit
!addr16.bit
PSW.bit
[HL].bit
ES:!addr16.bit
ES:[HL].bit
saddr.bit
sfr.bit
A.bit
!addr16.bit
PSW.bit
[HL].bit
ES:!addr16.bit
ES:[HL].bit
CY
CY
CY
Operands
Bytes
Table 30-5. Operation List (14/17)
3
3
2
3
2
3
3
3
2
4
3
2
5
3
3
3
2
4
3
2
5
3
2
2
2
Note 1 Note 2
1
1
1
1
1
2
2
2
1
2
4
2
3
3
2
2
1
2
4
2
3
3
1
1
1
Clocks
−
−
−
−
4
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
CY ← CY ∨ (saddr).bit
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
CY ← CY ∨ (ES, HL).bit
(saddr).bit ← 1
sfr.bit ← 1
A.bit ← 1
(addr16).bit ← 1
PSW.bit ← 1
(HL).bit ← 1
(ES, addr16).bit ← 1
(ES, HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
(addr16).bit ← 0
PSW.bit ← 0
(HL).bit ← 0
(ES, addr16).bit ← 0
(ES, HL).bit ← 0
CY ← 1
CY ← 0
CY ← CY
CPU
) selected by the system clock control
Operation
CHAPTER 30 INSTRUCTION SET
Z AC CY
×
×
Flag
×
×
×
×
×
×
×
×
×
×
1
0
×
878