UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 255

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Subsystem
clock
20 MHz internal
high-speed
oscillation clock
Before Change
CPU Clock
Internal high-
speed
oscillation clock
X1 clock
External main
system clock
20 MHz internal
high-speed
oscillation clock
Internal high-
speed
oscillation clock
X1 clock
External main
system clock
Subsystem
clock
After Change
Oscillation of internal high-speed oscillator
and selection of internal high-speed
oscillation clock as main system clock
• HIOSTOP = 0, MCS = 0
Stabilization of X1 oscillation and selection
of high-speed system clock as main
system clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
Enabling input of external clock from
EXCLK pin and selection of high-speed
system clock as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
Transition cannot be performed unless the
clock is changed to the internal high-speed
oscillation clock once.
• SELDSC = 0
Transition cannot be performed unless the
clock is changed to the internal high-speed
oscillation clock once.
Transition cannot be performed unless the
clock is changed to the internal high-speed
oscillation clock once.
Transition cannot be performed unless the
clock is changed to the internal high-speed
oscillation clock once.
(Set when changing the clock.)
Table 5-5. Changing CPU Clock (2/2)
Condition Before Change
XT1 oscillation can be stopped (XTSTOP
= 1)
20 MHz internal high-speed oscillation
clock can be stopped (DSCON = 0)
CHAPTER 5 CLOCK GENERATOR
Processing After Change
255

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