UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 587

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(3) SO latch
(4) Wakeup controller
(5) Serial clock counter
(6) Interrupt request signal generator
(7) Serial clock controller
(8) Serial clock wait controller
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
(10) Data hold time correction circuit
(11) Start condition generator
(12) Stop condition generator
Note Bit 0 is fixed to 0.
The SO latch is used to retain the SDA0 pin’s output level.
This circuit generates an interrupt request (INTIICA) when the address received by this register matches the
address value set to the slave address register (SVA) or when an extension code is received.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
This circuit controls the generation of interrupt request signals (INTIICA).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM bit)
• Interrupt request generated when a stop condition is detected (set by SPIE bit)
Remark
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
This circuit controls the wait timing.
These circuits generate and detect each status.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
This circuit generates a start condition when the STT bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY
bit = 1), start condition requests are ignored and the STCF bit is set to 1.
This circuit generates a stop condition when the SPT bit is set to 1.
2
C interrupt request is generated by the following two triggers.
Address: F0234H
WTIM bit:
SPIE bit:
Symbol
SVA
Bit 3 of IICA control register 0 (IICCTL0)
Bit 4 of IICA control register 0 (IICCTL0)
A6
7
Figure 15-4. Format of Slave Address Register (SVA)
After reset: 00H
A5
6
A4
5
R/W
A3
4
A2
3
CHAPTER 15 SERIAL INTERFACE IICA
A1
2
A0
1
0
Note
0
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