UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 625

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Note The wait time is calculated as follows.
Remark IICWL: IICA low-level width setting register
(IICWL setting value + IICWH setting value + 4 clocks) / f
IICWH: IICA high-level width setting register
t
f
F
CLK
:
D
:
SDA0 and SCL0 signal falling times
CPU/peripheral hardware clock frequency
IICBSY = 0?
MSTS = 1?
STCF = 0?
STT = 1
STT = 1
Wait
Wait
C
C
A
B
Note
Figure 15-29. Master Operation in Multi-Master System (2/3)
Yes
Yes
Yes
Enables reserving communication.
Disables reserving communication.
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
No
No
Prepares for starting communication
(generates a start condition).
Secure wait time
Prepares for starting communication
(generates a start condition).
Note
by software.
No
CLK
EXC = 1 or COI =1?
EXC = 1 or COI =1?
interrupt occurs?
interrupt occurs?
Slave operation
Slave operation
+ t
INTIICA
INTIICA
F
CHAPTER 15 SERIAL INTERFACE IICA
× 2
Yes
Yes
Yes
Yes
No
No
No
Waits for bus release
(communication being reserved).
Waits for bus release
Detects a stop condition.
D
625