UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 816

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
24.4.1 When used as reset
(1) When detecting level of supply voltage (V
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(a) When LVI default start function stopped is set (LVIOFF = 1)
•
•
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 210
<6> Wait until it is checked that (supply voltage (V
<7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
Figure 24-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <7> above.
When starting operation
When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
Cautions 1. Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after the
(default value).
register (LVIS).
• Operation stabilization time (10
• Minimum pulse width (200
2. If supply voltage (V
processing in <4>.
signal is not generated.
μ
s (MIN.))
DD
) ≥ detection voltage (V
DD
μ
s (MAX.))
)
DD
) ≥ detection voltage (V
CHAPTER 24 LOW-VOLTAGE DETECTOR
LVI
) when LVIMD is set to 1, an internal reset
μ
s).
LVI
)) by bit 0 (LVIF) of LVIM.
DD
816
))