UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 528

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
14.6.1 UART transmission
asynchronously (start-stop synchronization).
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remarks 1. f
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
UART performs the following four types of communication operations.
UART transmission is an operation to transmit data from the 78K0R/Lx3 microcontrollers to another device
Of two channels used for UART, the even channel is used for UART transmission.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
• UART transmission
• UART reception
• LIN transmission (UART3 only) (See 14.6.3.)
• LIN reception (UART 3 only)
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2. For 78K0R/LF3, UART0 is not mounted.
UART
f
MCK
CLK
: System clock frequency
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU0
TxD0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
None
5, 7, or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
UART0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
(See 14.6.1.)
(See 14.6.2.)
(See 14.6.4.)
Channel 2 of SAU0
TxD1
INTST1
UART1
CLK
Channel 0 of SAU1
TxD2
INTST2
/(2 × 2
CHAPTER 14 SERIAL ARRAY UNIT
11
UART2
× 128) [bps]
Note
Channel 2 of SAU1
TxD3
INTST3
UART3
528