UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 402

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(5) 12-bit A/D conversion result register (ADCR)
(6) 8-bit A/D conversion result register (ADCRH)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Cautions 2. To use voltage reference output to the positive reference voltage of the A/D converter, be sure to
Remark The combinations of the selectable reference voltage supplies (positive side, negative side) of the A/D
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
Symbol
This register is a 16-bit register that stores the A/D conversion result in the select mode. The higher 4 bits are fixed to
0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The
higher 4 bits of the conversion result are stored in FFF1FH and the lower 8 bits are stored in the FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 12-bit resolution are stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
ADCR
ADREF
0
0
1
1
Address: FFF1EH, FFF1FH
3. Do not change the output voltage of the reference voltage by using VRGV during the voltage
converter are as follows, according to the ADREF, VRSEL and VRON settings.
(ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC.
Using timing other than the above may cause an incorrect conversion result to be read.
0
set VRON to 1 after setting VRSEL to 1.
reference operation (VRON = 1).
VRSEL
0
Figure 10-9. Format of 12-bit A/D Conversion Result Register (ADCR)
0
1
0
1
0
VRON
Table 10-3. Settings of ADREF, VRSEL and VRON
FFF1FH
0
0
1
0
1
After reset: 0000H
AV
V
AV
V
REFOUT
REFOUT
Positive reference voltage of A/D
REFP
REFP
(VR output)
(VR output)
converter (AD
R
REFP
)
AV
AV
AV
AV
Negative reference voltage of A/D
SS
SS
REFM
REFM
CHAPTER 10 A/D CONVERTER
FFF1EH
converter (AD
REFM
)
402