UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 806

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(2) When LVI is ON upon power application (option byte: LVIOFF = 0)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
V
V
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-
Remark V
V
POR
PDR
LVI
(when X1 oscillation
oscillation clock (f
Internal high-speed
Internal reset signal
= 2.07 V (TYP.)
= 1.61 V (TYP.)
= 1.59 V (TYP.)
system clock (f
CPU
Supply voltage
High-speed
is selected)
2.
3.
4.
5.
1.8 V
Operation
VOLTAGE DETECTOR).
V
V
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
These are preliminary values and subject to change.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is less than 5.8 ms:
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is greater than 5.8 ms:
LVI
POR
PDR
(V
MX
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
Note 3
Note 1
Note 3
Note 3
IH
V
stops
DD
0 V
LVI
)
)
A POC processing time of about 2.1 to 6.2 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
A reset processing time of about 195 to 322
normal operation.
:
: POC power supply fall detection voltage
)
: POC power supply rise detection voltage
LVI detection voltage
Wait for oscillation
accuracy stabilization
Note 5
POC processing time
Reset processing time
oscillation clock)
(internal high-speed
(V
reset (default)
Normal operation
to be used for
LVI
Set LVI
specified by software
Starting oscillation is
= 2.07 V)
Note 4
and Low-Voltage Detector (2/2)
Note 2
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Reset processing time
(about 195 to 322 μs)
used for interrupt
Set LVI to be
DD
μ
≤ 5.5 V. To make the state at lower than 1.8 V reset state
oscillation clock)
(internal high-speed
s is required between reaching 2.07 V (TYP.) and starting
Normal operation
specified by software
Starting oscillation is
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Note 4
Note 2
(oscillation
Reset
period
stop)
(V
to be used for
reset (default)
Note 5
Wait for oscillation
accuracy stabilization
LVI
Set LVI
= 2.07 V)
oscillation clock)
(internal high-speed
POC processing time
Reset processing time
Normal operation
specified by software
Starting oscillation is
voltage (V
Change LVI
detection
Note 4
Note 2
LVI
)
Operation stops
806