UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 989

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Interrupt
functions
Function
IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H:
Interrupt request
flag registers
MK0L, MK0H,
MK1L, MK1H,
MK2L, MK2H:
Interrupt mask
flag registers
PR00L, PR00H,
PR01L, PR01H,
PR02L, PR02H,
PR10L, PR10H,
PR11L, PR11H,
PR12L, PR12H:
Priority
specification flag
registers
EGP0, EGP1:
External
interrupt rising
edge enable
registers, EGN0,
EGN1: External
interrupt falling
edge enable
registers
Software
interrupt request
acknowledgment
BRK instruction
Details of
Function
When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1).
manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the
compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three
instructions.
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the
flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
Be sure to clear bits 5, 6 of IF0H, bit 3 of IF1L, bit 3 of IF1H, bits 5 to 7 of IF2L, bits 0,
6, 7 of IF2H to 0. (78K0R/LF3)
Be sure to clear bit 3 of IF1H, bits 6, 7 of IF2H to 0. (78K0R/LG3)
Be sure to clear bits 6, 7 of IF2H to 0. (78K0R/LH3)
Be sure to set bits 5, 6 of MK0H, bit 3 of MK1L, bit 3 of MK1H, bits 5 to 7 of MK2L,
bits 0, 6, 7 of MK2H to 1. (78K0R/LF3)
Be sure to set bit 3 of MK1H, bits 6, 7 of MK2H to 1. (78K0R/LG3)
Be sure to set bits 6, 7 of MK2H to 1. (78K0R/LH3)
Be sure to set bits 5, 6 of PR00H and PR10H, bit 3 of PR01L and PR11L to 1.
(78K0R/LF3)
Be sure to set bit 3 of PR01H and PR11H, bits 5 to 7 of PR02L and PR12L, bits 0, 6,
7 of PR02H and PR12H to 1. (78K0R/LF3)
Be sure to set bit 3 of PR01H and PR11H, bits 6, 7 of PR02H and PR12H to 1.
(78K0R/LG3)
Be sure to set bits 6, 7 of PR02H and PR12H to 1. (78K0R/LH3)
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes
the IE flag to be cleared.
generated during execution of the BRK instruction, the interrupt request is not
acknowledged.
mov a, IF0L
and a, #0FEH
mov IF0L, a
Therefore, even if a maskable interrupt request is
When describing in C language, use a bit
Cautions
APPENDIX C LIST OF CAUTIONS
p.753
p.754
p.755
p.756
p.757
p.758
p.759
p.760
p.761
p.763
p.765
p.767
p.771
p.775
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