UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 822

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
24.4.2 When used as interrupt
(1) When detecting level of supply voltage (V
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(a) When LVI default start function stopped is set (LVIOFF = 1)
•
•
Figure 24-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <8> above.
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 210
<6> Confirm that “supply voltage (V
<7> Clear the interrupt request flag of LVI (LVIIF) to 0.
<8> Release the interrupt mask flag of LVI (LVIMK).
<9> Execute the EI instruction (when vector interrupts are used).
When starting operation
When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
(default value).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
register (LVIS).
“supply voltage (V
• Operation stabilization time (10
• Minimum pulse width (200
DD
) < detection voltage (V
μ
s (MIN.))
DD
) ≥ detection voltage (V
DD
μ
s (MAX.))
)
LVI
)” when detecting the rising edge of V
CHAPTER 24 LOW-VOLTAGE DETECTOR
LVI
)” when detecting the falling edge of V
μ
s).
DD
, at bit 0 (LVIF) of LVIM.
DD
DD
, or
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