UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 604

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.2 Addresses
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
matches the data values stored in the slave address register (SVA). If the address data matches the SVA values, the
slave device is selected and communicates with the master device until the master device generates a start condition or
stop condition.
15.5.3 Transfer direction specification are written to the IICA shift register (IICA). The received addresses are written
to IICA.
15.5.3 Transfer direction specification
a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is
receiving data from a slave device.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
The slave address is assigned to the higher 7 bits of IICA.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
INTIICA
INTIICA
SDA0
SCL0
SDA0
SCL0
Figure 15-17. Transfer Direction Specification
A6
A6
1
1
A5
A5
2
2
Figure 15-16. Address
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
A1
Transfer direction specification
A1
6
6
CHAPTER 15 SERIAL INTERFACE IICA
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note
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