UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 595

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark
Note When bit 3 (TRC) of the IICA status register (IICS) is set to 1 (transmission status), bit 5 (WREL) of
Condition for clearing (COI = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (TRC = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
• Cleared by WREL = 1
• When the ALD bit changes from 0 to 1 (arbitration
• Reset
• When not used for communication (MSTS, EXC, COI = 0)
<Master>
• When “1” is output to the first byte’s LSB (transfer
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
stop)
loss)
direction specification bit)
TRC
COI
0
1
0
1
IICA control register 0 (IICCTL0) is set to 1 during the ninth clock and wait is canceled, after which
the TRC bit is cleared (reception status) and the SDA0 line is set to high impedance. Release the
wait performed while the TRC bit is 1 (transmission status) by writing to the IICA shift register.
LREL:
IICE:
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Figure 15-7. Format of IICA Status Register (IICS) (2/3)
Bit 7 of IICA control register 0 (IICCTL0)
Bit 6 of IICA control register 0 (IICCTL0)
Note
(wait cancel)
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI = 1)
• When the received address matches the local
Condition for setting (TRC = 1)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
<Slave>
• When 1 (slave transmission) is input to the LSB
address (slave address register (SVA))
(set at the rising edge of the eighth clock).
(transfer direction specification bit) of the first byte
(during address transfer)
(transfer direction specification bit) of the first byte
from the master (during address transfer)
CHAPTER 15 SERIAL INTERFACE IICA
595