UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1012

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
3rd Edition
Edition
Modification of and addition of Note to Figure 14-98 Timing Chart of Stop
Condition Generation
Addition of Caution to 14.7.5 Calculating transfer rate
Modification of Note 2 in Table 14-4 Selection of operation clock
Addition of Caution 3 to Figure 15-3 Format of IICA Shift Register (IICA)
Modification of description in 15.2 (2) Slave address register (SVA)
Modification of description in Figure 15-4 Format of Slave Address Register
(SVA)
Addition of Note 3 to and modification of Caution in Figure 15-6 Format of IICA
Control Register 0 (IICCTL0) (1/4)
Addition of description to Figure 15-6 Format of IICA Control Register 0
(IICCTL0) (2/4)
Modification of description in Figure 15-6 Format of IICA Control Register 0
(IICCTL0) (3/4)
Addition of description to Figure 15-9 Format of IICA Control Register 1
(IICCTL1) (1/2)
Modification of 15.4.2 (1) Setting transfer clock on master side
Modification of Figure 15-23 Flow When Setting WUP = 0 upon Address Match
(Including Extension Code Reception)
Modification of Figure 15-24 When Operating as Master Device after Releasing
STOP Mode other than by INTIICA and deletion of Figure 15-25 When Operating
as Slave Device after Releasing STOP Mode other than by INTIICA (When Not
Required to Operate as Master Device) in old edition
Modification of 15.5.14 (1) When communication reservation function is enabled
(bit 0 (IICRSV) of IICA flag register (IICF) = 0)
Modification of Note 1 in Figure 15-27 Communication Reservation Protocol
Modification of Note in Figure 15-29 Master Operation in Multi-Master System
(2/3)
Modification of Figure 16-1 Block Diagram of LCD Controller/Driver
Addition of Caution 4 to and modification of Caution 5 in Figure 16-3 Format of
LCD Display Mode Register
Modification of Figure 16-4 Format of LCD Clock Control Register
Addition of Caution 5 to and modification of Figure 16-5 Format of LCD boost
level control register (VLCD)
Addition of <8> to 16.5 (2) Internal voltage boosting method
Addition of Caution to Figure 16-31 Examples of LCD Drive Power Connections
(External Resistance Division Method)
Modification of description in 19.2 Interrupt Sources and Configuration
Modification of Table 21-2 Operating Statuses in STOP Mode
Modification of Caution 1
Modification of Figure 22-1 Block Diagram of Reset Function
Modification of Table 22-1 Operation Statuses During Reset Period
Modification of Table 22-2 Hardware Statuses After Reset Acknowledgment
Modification of 22.1 Register for Confirming Reset Source
Modification of and addition of Caution 2 to Figure 22-5 Format of Reset Control
Flag Register (RESF)
Description
APPENDIX D REVISION HISTORY
CHAPTER 14 SERIAL
ARRAY UNIT
(continuation)
CHAPTER 15 SERIAL
INTERFACE IICA
CHAPTER 16 LCD
CONTROLLER/DRIVER
CHAPTER 19
INTERRUPT
FUNCTIONS
CHAPTER 21
STANDBY FUNCTION
CHAPTER 22 RESET
FUNCTION
Chapter
(10/11)
1012