UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 270

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F01B6H, F01B7H (TPS0)
Symbol
TPSm
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
Notes 1. When changing the clock selected for f
F01DEH, F01DFH (TPS1)
PRS
mk3
2. Only in the case of SDIV=0, CCSmn=1 and TISmn=1, continuously use of TAUm is allowed, even when
15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
2. k = 0, 1
3. mn: Unit number + Channel number
stop the timer array unit (TT0 = 00FFH, TT1 = 000FH).
changing CPU clock. However, the following limitation is existing.
• When changing CPU clock, source clock decrease/increase occurs as follows.
PRS
mk2
m = 0, 1, mn = 00 to 07, 10 to 13
14
CLK
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
: CPU/peripheral hardware clock frequency
Main clock → Subsystem clock (CSS = 0→1): −1 clock
Subsystem clock → Main clock (CSS = 1→0): +1 clock
PRS
mk1
13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Figure 6-6. Format of Timer Clock Select Register m (TPSm)
0
PRS
mk0
After reset: 0000H
12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
11
0
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
10
0
R/W
9
0
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.62 kHz
7.81 kHz
3.91 kHz
1.95 kHz
976 Hz
488 Hz
244 Hz
122 Hz
61 Hz
f
CLK
CLK
Selection of operation clock (CKmk)
= 2 MHz
(by changing the system clock control register (CKC) value),
8
0
PRS
m13
7
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.2 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.76 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
305 Hz
153 Hz
f
PRS
m12
CLK
6
= 5 MHz
PRS
m11
CHAPTER 6 TIMER ARRAY UNIT
5
PRS
m10
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.2 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.76 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
305 Hz
4
f
CLK
= 10 MHz
Notes 1,2
PRS
m03
3
PRS
m02
2
5 MHz
625 kHz
312.5 kHz
78.1 kHz
39.1 kHz
19.5 kHz
2.44 kHz
20 MHz
10 MHz
2.5 MHz
1.25 MHz
156.2 kHz
9.76 kHz
4.88 kHz
1.22 kHz
610 Hz
f
CLK
PRS
m01
= 20 MHz
1
PRS
m00
0
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