UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 629

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
An example of the processing procedure of the slave with the INTIICA interrupt is explained below (processing is
performed assuming that no extension code is used). The INTIICA interrupt checks the status, and the following
operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address does
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I
Remark
Interrupt servicing completed
not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns
from the interrupt (the ready flag is cleared).
remaining in the wait state.
INTIICA generated
Set ready flag
<1> to <3> above correspond to <1> to <3> in Figure 15-31 Slave Operation Flowchart (2).
SPD = 1?
STD = 1?
No
No
<3>
Figure 15-31. Slave Operation Flowchart (2)
Yes
Yes
<1>
<2>
Set communication mode flag
Communication direction flag
Clear ready flag
COI = 1?
← TRC
Yes
CHAPTER 15 SERIAL INTERFACE IICA
No
Clear communication direction
communication mode flag
flag, ready flag, and
2
C bus
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