UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 388

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
9.1 Functions of Clock Output/Buzzer Output Controller
supply to peripheral ICs.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The clock output/buzzer output controller is mounted onto all 78K0R/Lx3 microcontroller products.
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Figure 9-1 shows the block diagram of clock output/buzzer output controller.
Note
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ V
exceeding 5 MHz at V
f
MAIN
f
SUB
PCLOE1
PCLOE0
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
0
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
0
Prescaler
Prescaler
5
8
0
0
DD
3
8
< 2.7 V is prohibited.
Internal bus
f
Internal bus
f
0
MAIN
MAIN
0
f
f
MAIN
/2
/2
MAIN
f
f
SUB
SUB
11
11
CSEL1 CCS12 CCS11 CCS10
CSEL0 CCS02 CCS01 CCS00
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
to f
to f
to f
Clock output select register 0 (CKS0)
Clock output select register 1 (CKS1)
to f
to f
to f
MAIN
MAIN
MAIN
MAIN
SUB
SUB
/2
/2
/2
/2
/2
/2
13
13
4
7
7
4
Clock/buzzer
Clock/buzzer
controller
controller
PCLOE1
PCLOE0
Output latch
Output latch
(P31)
(P32)
PM31
PM32
PCLBUZ1
TI00/TO03/RTCDIV/
RTCCL/INTP2
PCLBUZ0
TI01/TO01/INTP5
DD
Note
Note
. Setting a clock
/P31/
/P32/
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