UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 252
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 252 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(12) CPU clock changing from 20 MHz internal high-speed oscillation clock (J) to internal high-speed oscillation
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(Setting sequence of SFR registers)
Status Transition
(J) → (B)
Status Transition
(D) → (C) (X1 clock: 2 MHz ≤
f
(D) → (C) (X1 clock: 10 MHz
< f
(D) → (C) (external main
clock)
X
≤ 10 MHz)
X
Notes 1. Set the oscillation stabilization time as follows.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
≤ 20 MHz)
clock (B)
Setting Flag of SFR Register
2. FSEL = 1 when f
(Setting sequence of SFR registers)
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
If a divided clock is selected and f
Setting Flag of SFR Register
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (5/6)
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
CLK
Register
Note 1
Note 1
Note 1
OSTS
> 10 MHz
CSC Register
MSTOP
Unnecessary if the CPU is operating with
CLK
0
0
0
≤ 10 MHz, use with FSEL = 0 is possible even if f
the high-speed system clock
SELDSC
Register
OSMC
0
FSEL
1
0/1
Note 2
0
DSCCTL Register
Must not be
Register
checked
checked
checked
Must be
Must be
OSTC
CHAPTER 5 CLOCK GENERATOR
Unnecessary
registers are
already set
MCM0
if these
1
1
1
DSCON
CKC Register
0
X
> 10 MHz.
CSS
0
0
0
252
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