UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 972

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Timer
array unit
Function
Changing values
set in registers
TOp,TOEp,
TOLp, and
TOMp during
timer operation
Default level of
TOpq pin and
output level after
timer operation
start
Operation of
TOpq pin in
combination
operation mode
(TOMpq = 1)
ISC: Input switch
control register
Collective
manipulation of
TOpq bits
Details of
Function
When TOEpq = 1, even if the output by timer interrupt of each timer (INTTMpq)
contends with writing to TOpq, output is normally done to TOpq pin.
Be sure to clear bits 5 to 7 to “0”.
Since the timer operations (operations of TCRpq and TDRpq) are independent of the
TOpq output circuit and changing the values set in TOp, TOEp, TOLp, and TOMp
does not affect the timer operation, the values can be changed during timer
operation. To output an expected waveform from the TOpq pin by timer operation,
however, set TOp, TOEp, TOLp, and TOMp to the values stated in the register setting
example of each operation.
When the values set in TOEp, TOLp, and TOMp (except for TOp) are changed close
to the timer interrupt (INTTMpq), the waveform output to the TOpq pin may be
different depending on whether the values are changed immediately before or
immediately after the timer interrupt (INTTMpq) signal generation timing.
The following figure shows the TOpq pin output level transition when writing has
been done in the state of TOEpq = 0 before port output is enabled and TOEpq = 1 is
set after changing the default level.
(a) When operation starts with TOMpq = 0 setting (toggle output)
(b) When operation starts with TOMpq = 1 setting (Combination operation mode
(a) When TOLpq setting has been changed during timer operation
(b) Set/reset timing
The setting of TOLpq is invalid when TOMpq = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TOpq pin is reversed.
(PWM output))
When TOMpq = 1, the active level is determined by TOLpq setting.
When the TOLpq setting has been changed during timer operation, the setting
becomes valid at the generation timing of TOpq change condition. Rewriting
TOLpq does not change the output level of TOpq.
The following figure (Figure 6-30) shows the operation when the value of TOLpq
has been changed during timer operation (TOMpq = 1)
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at
master channel timer interrupt (INTTMpq) generation is delayed by 1 count clock
by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave
channels are set as follows.
Cautions
APPENDIX C LIST OF CAUTIONS
p.290
p.298
pp.298,
299
pp.299,
300
p.302
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