UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 257

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
5.6.8 Conditions before clock oscillation is stopped
conditions before the clock oscillation is stopped.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remarks 1. The number of clocks listed in Table 5-7 to Table 5-9 is the number of CPU clocks before switchover.
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
Internal high-speed
oscillation clock
X1 clock
External main system clock
Subsystem clock
20 MHz internal high-speed
oscillation clock
Clock
2. Calculate the number of clocks in Table 5-7 to Table 5-9 by removing the decimal portion.
(f
(f
Set Value Before Switchover
CLK
CLK
Example When switching the main system clock from the internal high-speed oscillation clock to the
Table 5-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
= f
= f
0
1
MAINC
SUBC
)
CSS
)
Table 5-9. Maximum Number of Clocks Required in f
high-speed system clock (@ oscillation with f
f
f
1 + f
MAINC
MAINC
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
SELDSC = 0
(The main system clock is operating on a clock other than the 20 MHz
internal high-speed oscillation clock.)
IH
>f
>f
/f
SUBC
SUBC
MX
= 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
Conditions Before Clock Oscillation Is Stopped
2 + f
SUBC
(External Clock Input Disabled)
/f
MAINC
(f
CLK
clock
= f
0
MAINC
Set Value After Switchover
)
IH
CSS
= 8 MHz, f
1 + 2f
CHAPTER 5 CLOCK GENERATOR
MAINC
MAINC
(f
MX
/f
SUBC
CLK
= 10 MHz)
↔f
= f
clock
1
SUBC
SUBC
)
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
DSCON = 0
Flag Settings of SFR
Register
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