UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 967

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Clock
generator
Function
OSTC:
Oscillation
stabilization time
counter status
register
OSTS:
Oscillation
stabilization time
select register
CKC: System
clock control
register
DSCCTL: 20
MHz internal
high-speed
oscillation
control register
OSMC:
Operation speed
mode control
register
Details of
Function
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
Setting the oscillation stabilization time to 20
To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
The clock set by CSS, MCM0, SDIV, and MDIV2 to MDIV0 is supplied to the CPU
and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, timer array unit (when f
f
count clock), clock output/buzzer output, and watchdog timer) is also changed at the
same time.
CPU/peripheral operating hardware clock.
If the peripheral hardware clock is used as the subsystem clock, the operations of the
A/D converter and IICA are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
20 MHz internal oscillation can only be used if V
Set SELDSC when 100
The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1. p.225
Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing f
• Operating the DMA controller.
The CPU waits (140.5 clock (f
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of f
CPU is waiting.
To increase f
more clocks have elapsed.
Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
SUB
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is selected as the
CLK
Consequently, stop each peripheral function when changing the
to 10 MHz or higher, set FSEL to “1”, then change f
μ
s have elapsed after having set DSCON with V
CLK
)) when “1” is written to the FSEL bit.
CLK
Cautions
to a clock other than f
μ
s or less is prohibited.
DD
APPENDIX C LIST OF CAUTIONS
≥ 2.7 V.
X
can continue even while the
IH
.
CLK
DD
after two or
≥ 2.7 V.
SUB
/2,
p.220
p.222
p.222
p.222
p.222
p.222
p.222
p.224
p.224
p.225
p.225
p.228
p.228
p.228
p.228
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